Colliding Pulse Phase Detector for Picosecond Resolution Timing Measurement

single tap actually consists or four diodes distributed at 2 pS effective delay time along the line and tied together at the tap output. Fig. 2 shows the evolutio.n or the coincidence or two input pulses. The peak detector taps are biased such that neither the clock nor the trigger signal alone is large enough in amplitude to cause forward bias or the peak detector taps. This is the case at times To and T2. At time TI, however, there is coincidence or the two pulses and forward bias occurs. capturing a convolution or the two pulses on the tap hold capacitors. After a collision event is captured the outputs or the taps must be analysed. Digitising the tap outputs with comparators or ADCs is the preferred method of phase recovery. The present setup. however, does not yet include this tap processing circuitry. Instead, the response or the CPPD was measured using a steady state mixing technique. The clock is driven at a harmonic of the trigger input plus an offset. The response is filtered and displayed on a low frequency oscilloscope at the offset frequency. The waveforms shown in Fig. 3 are the outputs of two adjacent taps, spaced 8 pS apart in delay time. The change in hold capacitor voltage is seen on the oscilloscope as the trigger pulse is swept through the clock pulse at the tap. In steady state operation the CPPD has a peak output response or 20mV or output voltage change per picosecond or input phase shift. This is simply measured as the output signal slew rate achieved at each tap. The clock frequency used for the structure reported here was 7 GHz. The As computing and communication data rates move into the gigabit range, accurate phase and timing measurements of the associated integrated circuits become of critical importance. Phase shifters must be calibrated to picosecond accuracy, and digital systems now require clock skew and jitter measurements below lOpS. Current timing measurement techniques use oscillator based vernier circuits, ramp generator circuits or tapped delay line circuits for one shot phase capture.l-J Vernier circuits and ramp generator circuits have good resolution, but poor measurement rate or throughput due to the required wait time while the data are processed. Tapped delay line circuits have good throughput due to the distributed nature of the detector but poor resolution due to the present hybrid nature of their construction. We describe a colliding pulse phase detector (CPPD) consisting of a monolithic GaAs tapped delay line circuit with peak detector taps. The CPPD has the throughput advantages of the tapped delay line capture technique, with much finer resolution because it is integrated and uses a pulse conditioning technique...S to achieve short electrical transients. The CPPD has been fabricated and its operation verified by steady state testing. A response of better than 2OmV of output voltage swing on the detector hold capacitors has been achieved for 1 pS of trigger input phase shift. Response is currently limited by the input slew rates and the periodic filter fonned by the diode taps, and not the intrinsic speed of the taps themselves. When combined with preamps and analogue-to-digital convertors (ADCs) this circuit should be capable of high throughput, subpicosecond resolution phase detection in steady state or in single shot mode. The CPPD circuit shown in Fig. 1 consists of 128 pS of coplanar waveguide delay line integrated on a semi-insulating